This invention relates to electronic device fabrication processes and associated apparatus. More specifically, the invention relates to chemical vapor deposition processes for forming dielectric layers in high aspect ratio, narrow width recessed features.
It is often necessary in semiconductor processing to fill high aspect ratio gaps with insulating material. This is the case for shallow trench isolation, inter-metal dielectric layers, passivation layers, etc. As device geometries shrink and thermal budgets are reduced, void-free filling of high aspect ratio gaps (e.g., AR>3.0:1) becomes increasingly difficult due to limitations of existing deposition processes.
Most deposition methods either deposit more material on the upper region than on the lower region of a side wall or form cusps at the entry of the gap. As a result the top part of a high aspect ratio structure sometimes closes prematurely leaving voids within the gap's lower portions. This problem is exacerbated in small features. Furthermore, as aspect ratios increase, the shape of the gap itself can contribute to the problem. High aspect ratio gaps often exhibit reentrant features, which make gap filling even more difficult. The most problematic reentrant feature is a narrowing in the gap entrance caused by the etched side-walls sloping inward at the top. For a given high aspect ratio feature, this increases the ratio of gap volume to gap access area seen by the precursor species during deposition. Hence voids and seams become even more likely.
Going forward, the deposition of silicon dioxide assisted by high-density plasma chemical vapor deposition (HDP CVD)—a directional (bottom-up) CVD process—is the method of choice for high aspect ratio gap-fill. The method deposits more material at the bottom of a high aspect ratio structure than on its side-walls. It accomplishes this by directing charged dielectric precursor species downward, to the bottom of the gap. Thus, HDP CVD is not an entirely diffusion-based (isotropic) process.
Nevertheless, some overhang still results at the entry region of the gap to be filled. This results from the non-directional deposition reactions of neutral species in the plasma reactor and from sputtering/redeposition processes. The directional aspect of the deposition process produces some high momentum charged species that sputter away bottom fill. The sputtered material tends to redeposit on the side-walls. Thus, the formation of overhang cannot be totally eliminated and is inherent to the physics and chemistry of the HDP CVD process. Of course, limitations due to overhang formation become ever more severe as the width of the gap to be filled decreases, the aspect ratio increases, and the features become reentrant.
Fluorine species in the plasma have been observed to improve gap fill in HDP CVD processes. This improvement may be due to side-wall passivation and/or non-directional etching by elemental fluorine. Unfortunately, when fluorine remains in the deposited dielectric film, it can degrade film properties and electrical performance in the resulting product. Specifically, fluorine can diffuse to locations where it reacts with components or otherwise degrades electrical performance. It can also outgas to cause delamination of stacks and etch silicon to cause pits and voids. If the fluorine-containing dielectric is used for shallow trench isolation, fluorine diffusion can occur during subsequent high temperature process steps such as gate oxidation and activation anneals. The diffused fluorine may cause junction leakage, threshold voltage shifts, titanium fluoride formation to produce high resistance contacts, etc.
To improve fabrication of advanced technology devices, process fabrication technology requires better dielectric deposition processes that can fill high aspect ratio features of narrow width, without leaving gaps.